Mrs. Nagamani A N
Nagamani A N received M.Tech degree from VTU, Belagavi, INDIA and currently persuing Ph.D from VTU, Belagavi in the area of Reversible circuit optimization and Testing. She is working with PES Institute of Technology as Assistant Professor in Department of Electronics and Communication Engineering. Her area of research includes, Reversible logic optimization and testing, low power Digital VLSI and Analog and mixed signal design. She has published several publications in the above mentioned areas in the peer reviewed conferences and Journals."
Electronics & Communications
- SPIRIT - Process co-ordinator
- Department Time table co ordinator
- Department Practical exam co-ordinator
- Subject Anchor
Expertise / list of subjects handled
- CMOS VLSI design, Digital System design using VHDL and Verilog, Analog and Mixed mode VLSI Design, Analog Electronics, Linear Integrated circuits, Solid state Devices, Low Power VLSI design, High speed Digital Design, Network Analysis and synthesis, Testing of Digital VLSI circuits, Synthesis and optimization of Digital circuits, Field Theory, Transmission lines and Waveguides
- VLSI Design Verification, Low power VLSI design, Synthesis and optimization of Digital circuits, Testing and verification of Digital circuits, Advanced microcontrollers
- Primary Research area in Digital VLSI Design, Mixed signal design, Testing of digital circuits specially Reversible circuits. Other interests include Digital design FPGA prototyping and low power and high speed Digital VLSI designs
- Nagamani A N and Nishchai S “ High performance Quaternary Arithmetic logic unit” at 14th Euromicro Conference on Digital System Design 2011, Finland, Europe, held during August – Sept 2011, published in IEEE digital library. 978-0-7695-4494-6/11 $26.00 © 2011 IEEE DOI 10.1109/DSD.2011.23
- Nagamani A N and Shivanand B K “Design and Performance evaluation of Hybrid Prefix Adder and Carry Increment Adder in 90nm regime” at International Conference on Nanoscience, Engineering and Technology (ICONSET-2011) at Sathyabhama university , Chennai , INDIA ( publication in IEEE) held during 28th- 30th November 2011, 978-1-4673-0073-5/11/$26.00 @2011 IEEE
- Nagamani A N and Santhosh Sanjeevannanavar “Efficient Design and FPGA Implementation of JPEG Encoder using Verilog HDL” at International Conference on Nanoscience, Engineering and Technology (ICONSET-2011) at Sathyabhama university , Chennai , INDIA ( publication in IEEE) held during 28th- 30th November 2011, 978-1-4673-0073-5/11/$26.00 @2011 IEEE
- Mahadevana Gowda J K, Nagamani A N, Lokesha K “An Improved Minimum Blind Zone Nonlinear Phase Frequency Detector to achieve a Fast Locking in PLLs” 2012 International Conference on Electronics Computer Technology (ICECT 2012), kanyakumari ,INDIA.978-1-4673-1850-1/12/$31.00 © 2012 IEEE
- Nagamani A N and Vinod Kumar Agrawal “Design and Analysis of variable cost Bypass Multiplier using Reversible Logic” at IEEE International conference ICRDPET March 2013, EGS Pillay Engineering College, Nagapattinam, INDIA
- Nagamani A N and Supreetha N J ,” Design of online testable fast divider”, at IEEE International conference C2SPCA, Oxford college of Engineering, Bangalore, INDIA, October 2013.
- Nagamani A N and Rohith G M “ Design, Analysis and implementation of Parallel prefix based modulo 2n-1 adders” at Elsevier International conference on Communication and Computing, ICC 2014, at Alpha college of Engineering, Bangalore, INDIA, June 12-14, 2014.
- Nagamani A N and Vinod Kumar Agrawal, “ Design of Quantum cost and delay optimized Wallace tree multiplier” at Springer International conference on Artificial Intelligence And Evolutionary Algorithms In Engineering Systems ICAEES, NIU, Kumaracoil, Tamilnadu, April 2014.
- Nagamani A N, Vinod Kumar Agrawal, Ramya M Bhat, Shrilakshmi N K Vijaya K Sonnad,” Design and Analysis of ESOP based Online Testable Reversible SRAM Array”, at International Conference on Advances in Electronics, Computers and Communications (ICAECC) October 10 – 11, 2014, Bangalore, India.
- Nagamani A N and Nishchai S “Delay optimized Quaternary ALU” at N4C11, RVCE, Bangalore in April 2011
- Girish S and Nagamani A N “Network router implementation – IPV4 and IPV6 addressing” at NCSCV 2013, 5th National Conference on Signal processing Communication and VLSI design.
- Nagamani A N, Anuktha S Nayak, Nandita N, Vinod Kuar Agrawal, “A Genetic Algorithm based Heuristic method for test set generation in Reversible circuits” Accepted in IEEE Transactions on Computer Aided design of Integrated circuits and systems, March 2017 ( Published in Early access)
- A N Nagamani, Chirag Ramesh, Vinod Kumar Agrawal, Design of optimized Reversible Squaring and Sum-of-Squares Units,In Journal of Circuits, Systems and Signal Processing (CSSP), Springer, 2017. (Accepted)
- Nagamani A N, Ashwin S, Abhishek B, Vinod Kumar Agrawal, “ An exact approach for complete test set generation of Toffoli-Fredkin and Peres based Reversible circuits”, Springer Journal of Electronic testing vol. 32(2), pages 175-196, 2016
- Nagamani A N, Ashwin S, Abhishek B, Vinod Kumar Agrawal, “ Design and Analysis of multiple parameter optimized n-bit reversible comparator” Journal of Circuits systems and computers, pp-1650112,World scientific publishing corporation, USA,2016
- Himanshu Thapliyal, Jayashree HV,Nagamani A N, Hamid R Arabnia,”Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder”, Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97 , 2013
- Nagamani A N, Vinod Kumar Agrawal, Shruti J Bhat, Vandana J, Vidya V,”On the Design of Hazard free Reversible Asynchronous Circuits”, at International Conference on Advances in Electronics, Computers and Communications (ICAECC) October 10 – 11, 2014, Bangalore, India.
- Nagamani A N, Ashwin S, Vinod Kumar Agrawal “Design of Optimized Reversible Binary adder/Subtractor and and BCD Adders” IC3I, held during ,27-29 November 2014, Mysore, INDIA.
- Nagamani A N, Ashwin S, Vinod Kumar Agrawal “Design of Optimized Reversible Binary and BCD Adders” at VLSI SATA, held during ,8-11 January 2015, Mysore, INDIA
- Nagamani A N, Manu S, Vinod Kumar Agrawal “Design of Priority Encoding based Reversible Comparators” at IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2015) held during 1 - 4 June 2015, NTU, SINGAPORE.
- Nagamani A N, Nikhil Reddy, Vinod Kumar Agrawal, “Design and Analysis of Reversible Binary and BCD Adders” at Springer - ICMEET 2015 to be held during December 18-19, 2015, Visakapatanam, INDIA
- Nagamani A N, Vishnuprasad H, Rajendra Hathwar, Vinod Kumar Agrawal, “Design of Optimized Reversible Multiplier for High Speed DSP Application” at ICICS 2015, to be held at Nanyang Technological university, Singapore, during December 2 - 4, 2016.Publisher : IEEE
- Chandana V , Navya C, Nagamani A N and Vinod Kumar Agrawal, “Design of Register File using Reversible Logic” at IEEE International conference ICCPCT-2016, NUICE, Kanyakumari, INDIA during 18-19 March, 2016. Publisher : IEEE
- Nagamani A N, Nikhil R, Manish Nagaraj, Vinod Kumar Agrawal, “ Reversible Radix-4 Booth multiplier for DSP applications”, at IEEE International conference on Signal processing and Communications held at Indian Institute of Science, Bangalore, INDIA during 12-15 June 2016. Publisher : IEEE
- Nagamani A N, Desik Rengarajan, Vinod Kumar Agrawal,”An optimized design of reversible magnitude and signed comparators” in International conference on Electron devices and solid state circuits, held at University of HongKong, HongKong, August 2016.
- Nagamani A N, Kavyashree C K, Saraswathy RM, Kartika CH V and Vinod Kumar Agrawal “Design of Reversible Floating Point Adder for DSP Applications” at Springer International conference ICSNCS-2016, JNU, New Delhi, INDIA during 24-26 Feb, 2016. Publisher: Springer