Mr. Utpal Desai

Assistant Professor

22+ years of experience in microprocessor VLSI design with Intel Santa Clara (1993-2003) and Intel Bangalore Design Centre (2003-2016), spanning across custom digital circuit design, physical integration, design methodology development, product management and post silicon debug. 2+ years, Principal Engineer at Qualcomm (India), Leading Clk Lib Physical Design, driving multiple initiatives to aid post silicon PDN debug. methodologies to enable per part/per rail optimal Voltage settings in Production to save tester time, and production vector count reduction for post silicon characterization time improvement. Areas of expertise include high speed custom digital circuit design, clock generation and distribution architectures, cross clock-domain communication protocols, standard cell library design, high speed and low power custom flip-flops, physical integration tools/flows/methodologies, low power design methodologies, mixed signal validation and post silicon functional/speed debug

Electronics & Communications


Qualification Institution Year