Dr. Suryaprasad J

Vice Chancellor

Qualification Institution Year
B.E, M.Tech, Ph.D

Designation Institution From To
Vice Chancellor PES University, Bangalore 2020
Director & Principal PES School of Engineering, Bangalore 2005 2020
Senior Software Engineer/Technical Manager Motorola CorTech , iDEN Advance Technology Group, Plantation, FL 2004 2005
Research Assistant Motorola, Inc., iDEN Subscriber Group, Ft. Lauderdale, FL 2003 2003
Senior Member of Technical Staff Cadence Design Systems, Inc., San Jose, CA 2002 2003
Florida Teaching Assistant Department of Computer Science & Engineering 1999 2003
Professor (On Study Leave) P E S Institute of Technology, Bangalore 1999 2005
Assistant Professor P E S Institute of Technology, Bangalore 1993 1999
Lecturer D S College of Engineering, Bangalore 1989 1993
Responsibilities Held
  • Technical lead in developing a virtual platform for simulating and modeling iDEN next generation cellphones to enable reduction in design cycle time. Tasks involved development, leading a group of 18 technical members, and coordinating work with two 3rd party groups. Contributions include developing the Statement Of Work for the project, developing IP modules at high level of abstraction, Verification and System Integration. The project was successfully implemented ahead of schedule aiding in reduction of over 10% of total design cycle time of next generation cellphone being developed. Successfully showcased many usecases including the dual processor based cellphone bootup sequence for WinCE and Linux. Presented and demoed internally at the Motorola – QTIPS’04.
  • Key contributor in developing SystemC based methodology for Hardware Software co-design of Embedded Systems.
  • Developed the complete Test plan and execution for the testing of Arm Design Kit(ADK) and ISS integration. Reported, Tested and Verified bugs using PCR system.
  • Worked on LDV4.2 (NC-SC) project in Systems Design and Verification group. Was involved in developing SystemC based model at different levels of abstractions for demo reference design.
  • Developed and delivered SystemC Quick-start workshop for R&D group at Cadence.
  • Developed training material for Educational Services on Virtual Component Co-design (VCC).
  • Developed and delivered a 1 day workshop on VCC at Motorola, Plantation, Florida. Summer Intern, Cadence Design Systems, Inc., San Jose, CA: May 2001 – Aug 2001
  • Using Virtual Processor Modeling (VPM) technique studied Software Estimation of MPC555 processor. Developed C++ code for the same.
  • Offered undergraduate courses in CAD Based Computer Design, VLSI Design, Data Structures & Algorithms, Introduction to MicroComputers (Motorola 68000), Foundations of Computer Science
  • Offered a course on Software Hardware Co-design using VCC for both graduate and under-graduate students jointly with Prof. Ravi Shankar.
  • Co-authored two NSF project proposals with Prof. Ravi Shankar, FAU, USA
  • Offered various Computer Science & Engineering courses at both graduate and under-graduate level
Research Interest
  • System level design methodologies
  • Hardware Software Co-design
  • Embedded System Design
  • Power Optimal Design
  • Verification Methodologies
  • Verification Methodologies

  • Sushil Menon, Jayadevappa, S., “A Pattern Based Methodology for the Design and Implementation of Multiplexed Master-Slave devices at the System-Level Use-case: Modeling a Level-2 Cache IP module at Transaction Level”, IEEE NESEA 2010, Suzhou, China Nov 24,25, 2010.
  • Jayadevappa, S., Deepa, S., “GC 2010-6 THE NEXT GENERATION ENGINEER EXPECTATIONS, CHALLENGES & OPPORTUNITIES ! A SIMPLE CASE STUDY IN INDIAN CONTEXT", 2010 ASEE, 9th Global Colloquium on Engineering Education, , Singapore Oct 18-21, 2010.
  • Jayadevappa, S., Arvind Ravi., Bajarangbali R., Vivekanada B., Nimish Pawar, & Rajesh, “GC 2010-104: EMBEDDED BASED REMOTE ACCESS ANALOG ELECTRONICS LABORATORY”, 2010 ASEE, 9th Global Colloquium on Engineering Education, , Singapore, Oct 18-21, 2010.
  • Jaydevappa, S., Shankar, R., “The Changing Ways of Computer Science & Engineering Education: A Suitable Pedagogy to Adapt Better”, ASEE’09, Austin, Texas June14-17, 2009.
  • Jaydevappa, S., Shankar, R., “The Changing Ways of Computer Science & Engineering Education: A Suitable Pedagogy to Adapt Better”, ASEE’09, Austin, Texas June14-17, 2009.
  • Thilak Kumar, Rashmi L S, Suryaprasad J., “Interactive Response System”, International Conference On Management Technology For Educational Practices, MTEP 2009, Bangalore.
  • Jayadevappa,S., Shankar,R., and Mahgoub,I., “A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study”, ISVLSI ’04, Lafayette, LA, February 19-20, 2004.
  • Jayadevappa,S., Mahgoub,I., and Shankar, R., “Experiences Of Modeling Soft IP’S At High Level Of Abstraction Using SystemC: A Case Study”, Design and Verification Conference, 2004, San Jose, March 1-3.
  • Jayadevappa,S., and Shankar, R., “CAD Based Design Course Using State Of The Art System Level Language”, ASEE 2004 Annual Conference, Salt Lake City, Utah, June 20 – 23, 2004. Nominated for Best Paper Award.
  • Shankar, R., Jayadevappa, S., “A New SystemC-based Foundation for the CE curriculum”, EWME’04, Lausanne, Switzerland, April 14-15, 2004.
  • Rajeevlochanam,J., Jayadevappa,S., and Shankar,R., “High Level Performance Modeling using VCC”, ICU conference 2002, San Jose, September 15-19, 2002.
  • Shankar,R., Jayadevappa,S., and Hsu,S., “Hardware Implementation of Rendezvous Inter-Process Communication with Round Robin Scheduling: Prototype two processes”, KES 2001, Osaka, Japan, September 6-8, 2001.
  • Talati,A., Pandya,A., Tokodo,T., and Jayadevappa,S., “ Foreign Currency Prediction using Time Series Prediction” SPEC’00, Orlando, June 14-16, 2000.
  • Delivered an invited lecture on “Virtual Prototyping in SoC based Design – Is this the Need of the hour?” at IEEE Communications Society, Palm Beach Chapter, 2004.

  • Sushil Menon, Jayadevappa S., “A Novel System-Level Methodology for the Design and Implementation of Multiplexed Master-Slave System-on-Chip components using Object-Oriented Patterns”, International Journal of Design, Analysis and Tools for Integrated Circuits and Systems, Vol. 2, No. 1 Link: http://ijdatics.distributedthought.com/current_issues.html Online Version Available: 19 August 2011 ISSN: 2071-2987(online version), 2223-523X (print version)